1. Technical Field
The present disclosure relates to decoding in communication systems.
2. Background Information
FIG. 1 (Prior Art) is a diagram of one type of conventional wireless communication system that communicates packets. Packets 1 of data can be communicated from a first wireless communication device 2 to a second wireless communication device 3. Communication device 3 includes an antenna 4, a RF transceiver integrated circuit 5, and a digital baseband integrated circuit 6. Digital baseband integrated circuit 6 includes a number of parts including an Analog-to-Digital Converter (ADC) 7, a receive path 8, a Digital-to-Analog Converter (DAC) 9, a transmit path 10, an interrupt controller mechanism 11, and a processor 12. The incoming packets 1 are received on antenna 4, and pass through RF transceiver 5, and ADC 7, and into the receive path 8. Within the receive path 8, the packets pass through a number of processing blocks including a Fast Fourier Transform (FFT) processing block 13, a demodulator block 14, and a decoder block 15. The packets are often not communicated as complete packets, but rather the payload of the packet is broken into portions. Each portion may be called a “sub-packet”. Each sub-packet may have its own Cyclic Redundancy Check (CRC) value that is usable to determine whether the data payload of the sub-packet has been received correctly. The data payloads of all the sub-packets may in turn be assembled, and the assembled payload may be checked using another CRC value. In the example of FIG. 1, the checking of CRC values occurs in decoder block 15.
FIG. 2 (Prior Art) illustrates a timeline of processing of a set of such sub-packets SP1-SP5 in decoder block 15 of FIG. 1. Each sub-packet has its own CRC value as illustrated. If all the sub-packets are properly received as determined in decoder block 15 using the CRC values, and if the overall packet data payload is determined to have been properly received by decoder block 15, then decoder block 15 interrupts the processor 12. Such an interrupt may, for example, be communicated via signal conductor 16 to interrupt controller 11 that in turn interrupts processor 12 in conventional fashion. Once interrupted, processor 12 handles the received packet of data as appropriate. It is generally not desirable to interrupt the processor frequently because interrupting the processor slows the processor from performing other tasks. Consequently, FIG. 2 shows only one interrupt being generated even though a sequence of sub-packets SP1-SP5 has been received. The interrupt is represented by vertical arrow 17. Over time, higher data throughput rates have been required in wireless communication systems. Supporting such higher data throughput rates has burdened the processing capabilities of various portions of the circuits of wireless communication devices such as devices 2 and 3. Solutions are desired.